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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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DBusSimplePlugin's Wishbone support forces 32-bit reads #426

Closed kivikakk closed 2 months ago

kivikakk commented 3 months ago

I notice that DBusSimplePlugin's Wishbone bridge forces all reads to appear to be 32-bits wide:

https://github.com/SpinalHDL/VexRiscv/blob/0af9894e698288d65f6127c4a2806986dbabf09c/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala#L197-L199

I'm not sure of the exact reason it was done this way, but I'm wondering if you'd be amenable to changing this default! For some MMIO it's helpful to be able to distinguish the read size.

Dolu1990 commented 3 months ago

Hmm i think you are right, this shouldn't be necessary to have this force to "1111" Can you give a try without those 3 lines ?

kivikakk commented 3 months ago

Yes, in fact I'm doing that on my fork, and it works perfectly well! I'll make a PR if you like?

Dolu1990 commented 3 months ago

Sure thanks ^^