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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
2.52k stars 420 forks source link

DBusSimplePlugin: don't force SEL to 1111 on read. #427

Closed kivikakk closed 2 months ago

kivikakk commented 3 months ago

Closes #426.

Thanks! :)

Dolu1990 commented 2 months ago

thanks ^^

kivikakk commented 2 months ago

Thanks! 🐱