SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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Verilator expects `-std=c++14` #431

Closed goekce closed 1 month ago

goekce commented 1 month ago

I stumbled upon the following error when following https://github.com/SpinalHDL/VexRiscv/tree/master?tab=readme-ov-file#murax-soc using Verilator 5.028:

$ make clean test
error: #error "Verilator requires a C++14 or newer compiler"

The following makefiles still use -std=c++11:

..VexRiscv $ grep -ri c++11
src/test/cpp/briey/makefile: ...
src/test/cpp/regression/makefile ...
src/test/cpp/murax/makefile ...

The simulation works when I remove -CFLAGS—std=c++11. If a maintainer confirms, I can create a PR.

Related:

Dolu1990 commented 1 month ago

I can create a PR.

Sure :) Thanks