add Murax config with native jtag based on the docs

[goekce]

I will use the native Jtag on AMD FPGAs often, so I created a Murax config according to the docs in:

https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag

It was my first experience with Scala. I would be glad to hear your feedback on whether my approach with ifGen is plausible. I had doubts about whether I should create an independent class or not.

[Dolu1990]

Hi ^^

That should be fine. The one down side is that :

          val jtagCtrl = JtagTapInstructionCtrl()
          val tap = jtagCtrl.fromXilinxBscane2(userId = 2)

Will not get named in the verilog because it isn't captured as a reference in the component (it is only captured in the "case" scope)

Instead, it could be defined next the were the val jtag is defined as following :

val jtagNative = withNativeJtag generate new ClockingArea(debugClockDomain){
  val jtagCtrl = JtagTapInstructionCtrl()
  val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
}

Then those can be used from the "case" statment ^^ Note i used a xxx generate yyy instead of a ifGen. both are equivalent.

[goekce]

That should be fine.

You probably refer to my approach with ifGen, no?

I indeed could not find any jtagNative string in the generated code Murax.v. Now I moved the names outside and they are visible.

I believe they don't belong to val io because io is only for generating the interface signals, right?

Is this what you recommended?

[Dolu1990]

You probably refer to my approach with ifGen, no?

Ahh the whole PR ^^

I believe they don't belong to val io because io is only for generating the interface signals, right?

Yes right, io is just for the component in/out

Look all good. Thanks :D