DPC and DCSR csrs for enabling Semihosting

shufps commented 5 years ago

I tried to enable semihosting on the VexRiscV and noticed that the only thing which prevents semihosting from working are the missing DPC and DCSR csrs.

I grepped through the code but couldn't fine any implementations for it, unfortunately.

Afaik DPC is the last PC when the ebreak instruction was executed - and it is therefore the same as the PC if I figured out this correctly. So I could query the PC and could live with it.

The DCSR contains reason-flags. Especially the DCSR_EBREAKM flag would be the only flag needed for actually using semihosting.

There already is an implementation in openocd for semihosting for RISC-V, it could be easily used for the VexRiscV - but I don't know how to implement the flag.

Please, could you give me some tipps, how to do it?

shufps commented 5 years ago

ah wait ... perhaps we neither need DPC nor DCSR ... alone with the PC it's possible to figure out if it was a semihosting ebreak like it is done in riscv_semihosting.c from openocd:

if (pre != 0x01f01013 || ebreak != 0x00100073 || post != 0x40705013) {
    /* Not the magic sequence defining semihosting. */
    return 0;
}

or as assembly-code:

slli x0, x0, 0x1f 
ebreak
srai x0, x0, 0x7

I'll test this and keep you up-to-date

shufps commented 5 years ago

Aaaah, yes ... it's working lol ...

There are still issues left (like crashing after output of the text) but this should be quite minor to fix

shufps commented 5 years ago

Ah it seems to be now working ... steping-over and running-over the semihosting call seems to work without crashes or other strange behaviour.

I'll clean everything up and open a PR on mondays^^

shufps commented 5 years ago

PR is done in the vexriscv openocd-version. Closing this issue.

SpinalHDL / VexRiscv

DPC and DCSR csrs for enabling Semihosting #89