How to blackbox `tilelink.fabric.RamFiber` in MicroSoc?

[Jzjerry]

Hi,

I'm trying to synthesize the MicroSoc onto an ice40 FPGA, and I found that the RamFiber in MicroSoc is a single-port RAM, which should be able to be wrapped into the SPRAM IP of ice40. So, I tried to blackbox it directly using:

    val ram = new tilelink.fabric.RamFiber(6 KiB)
    ram.up at 0x80000000l of sharedBus
    ram.thread.logic.mem.generateAsBlackBox()

and added .addStandardMemBlackboxing(blackboxOnlyIfRequested) when generating the soc. However, it resulted in the error:

[info] [Warning] Elaboration failed (0 error).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 0.371 : Elaborate components
[info] The main thread is stuck at :
[info]     sun.misc.Unsafe.park(Native Method)
[info]     java.util.concurrent.locks.LockSupport.park(LockSupport.java:175)
[info]     java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2039)
[info]     java.util.concurrent.CyclicBarrier.dowait(CyclicBarrier.java:234)
[info]     java.util.concurrent.CyclicBarrier.await(CyclicBarrier.java:362)
[info]     vexiiriscv.soc.demo.MicroSoc$$anon$2.<init>(MicroSoc.scala:79)
[info]     vexiiriscv.soc.demo.MicroSoc.$anonfun$main$1(MicroSoc.scala:59)
[info]     vexiiriscv.soc.demo.MicroSoc$$Lambda$92/1187777398.apply(Unknown Source)
[info]     vexiiriscv.soc.demo.MicroSoc.<init>(MicroSoc.scala:59)
[info]     vexiiriscv.soc.demo.MicroSocGen$.$anonfun$report$1(MicroSoc.scala:110)
[info]     vexiiriscv.soc.demo.MicroSocGen$$$Lambda$10/146611050.apply(Unknown Source)
[info] ! SpinalHDL async engine is stuck !
[error] Exception in thread "main" java.lang.ArrayIndexOutOfBoundsException: 0
[error]         at spinal.core.ScalaLocated$.short(Trait.scala:607)
[error]         at spinal.core.ScalaLocated.getScalaLocationShort(Trait.scala:591)
[error]         at spinal.core.ScalaLocated.getScalaLocationShort$(Trait.scala:591)
[error]         at spinal.core.fiber.Handle.getScalaLocationShort(Handle.scala:35)
[error]         at spinal.core.fiber.EngineContext.$anonfun$start$13(AsyncCtrl.scala:118)
[error]         at spinal.core.fiber.EngineContext.$anonfun$start$13$adapted(AsyncCtrl.scala:117)
[error]         at scala.collection.TraversableLike$WithFilter.$anonfun$foreach$1(TraversableLike.scala:985)
[error]         at scala.collection.mutable.LinkedHashMap.foreach(LinkedHashMap.scala:152)
[error]         at scala.collection.TraversableLike$WithFilter.foreach(TraversableLike.scala:984)
[error]         at spinal.core.fiber.EngineContext.start(AsyncCtrl.scala:117)
[error]         at spinal.core.fiber.Engine$.create(AsyncCtrl.scala:175)
[error]         at spinal.core.internals.PhaseCreateComponent.impl(Phase.scala:2554)
[error]         at spinal.core.internals.PhaseContext.doPhase(Phase.scala:182)
[error]         at spinal.core.internals.SpinalVerilogBoot$.$anonfun$singleShot$12(Phase.scala:2930)
[error]         at spinal.core.internals.SpinalVerilogBoot$.$anonfun$singleShot$12$adapted(Phase.scala:2928)
[error]         at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error]         at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error]         at spinal.core.internals.SpinalVerilogBoot$.$anonfun$singleShot$7(Phase.scala:2928)
[error]         at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:71)
[error]         at spinal.core.internals.SpinalVerilogBoot$.singleShot(Phase.scala:2864)
[error]         at spinal.core.internals.SpinalVerilogBoot$.apply(Phase.scala:2859)
[error]         at spinal.core.Spinal$.apply(Spinal.scala:414)
[error]         at spinal.core.SpinalVerilog$.apply(Spinal.scala:432)
[error]         at vexiiriscv.soc.demo.MicroSocGen$.delayedEndpoint$vexiiriscv$soc$demo$MicroSocGen$1(MicroSoc.scala:108)
[error]         at vexiiriscv.soc.demo.MicroSocGen$delayedInit$body.apply(MicroSoc.scala:106)
[error]         at scala.Function0.apply$mcV$sp(Function0.scala:39)
[error]         at scala.Function0.apply$mcV$sp$(Function0.scala:39)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
[error]         at scala.App.$anonfun$main$1$adapted(App.scala:80)
[error]         at scala.collection.immutable.List.foreach(List.scala:431)
[error]         at scala.App.main(App.scala:80)
[error]         at scala.App.main$(App.scala:78)
[error]         at vexiiriscv.soc.demo.MicroSocGen$.main(MicroSoc.scala:106)
[error]         at vexiiriscv.soc.demo.MicroSocGen.main(MicroSoc.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1

Could you tell me the correct way of blackboxing the RAM?

Thanks!

[Dolu1990]

Hi,

The main thread is stuck at :

Mean that you are blocking the elaboration thread by accessing something too early

(the SoC elaboration use a multithreaded negociation framework)

You can do instead an area of code for all the late patches :

val patches = Fiber build new Area{
  ram.thread.logic.mem.generateAsBlackBox()
}

[Jzjerry]

Cool, it's working now! Thanks a lot!