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SpinalHDL / VexiiRiscv

Like VexRiscv, but, Harder, Better, Faster, Stronger
MIT License
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Shallower Pipeline for VexiiRiscv? #14

Open Jzjerry opened 6 months ago

Jzjerry commented 6 months ago

Hi,

Back in VexRiscv there are options like NoMemory and NoWriteBack that can be toggled for shallower pipeline structures (below 5 stages), which is pretty useful in reducing FFs.

I noted that in VexiiRiscv the plugins are pretty much categorized in a 5-stage manner, and it seems there are no similar options that shorten the pipeline. Is it possible to have a pipeline structure below 5 stages here?🤔

Dolu1990 commented 6 months ago

Hi ^^ Things are kinda handled differently with VexiiRiscv.

Mostly, the lenght of the different VexiiRiscv pipeline grow on demand. For instance, the LSU cacheless plugin can be parametrized to only use execute 0 + execute 1 : https://github.com/SpinalHDL/VexiiRiscv/blob/4d2ff4b29d04bf033239ace06fb0f61b3600362d/src/main/scala/vexiiriscv/execute/lsu/LsuCachelessPlugin.scala#L35 By setting wbAt to 1 instead of 2.

Same for the MulPlugin, Fetch plugins and so on

So in other words, it is all about how the plugins are parametrized.

Currently there is no example to get less than 5 stages.