SpinalHDL / VexiiRiscv

Like VexRiscv, but, Harder, Better, Faster, Stronger
MIT License
63 stars 7 forks source link

Fix random sim fails, add assert messages #3

Closed andreasWallner closed 6 months ago

andreasWallner commented 6 months ago

StreamDriver does not drive the ready signal before the first clock edge, which can trigger the assertion in the LsuCachelessPlugin. Drive at simulation start to prevent that.

Add assert message to make it easier to debug regression fails caused by them.

Dolu1990 commented 6 months ago

Ahhhh lolol Thanks :D