Closed xobs closed 6 years ago
Thanks ! I will check all of that.
So it look good, i should realy implement a continuous integration XD
On your side, i remember you said that software breakpoint were not working, is that fine now ? (it isn't related to this pull request)
I believe software breakpoints were due to me not understanding the limitations of the system -- I was trying to add breakpoints to instructions in ROM, which doesn't work due to how they're implemented. They're working fine now!
Cool ^^
We're using a Vexriscv core in the NeTV2 project via the
litex
umbrella of projects. This project uses Etherbone vialiteeth
, which exposes the Wishbone bus over Ethernet, PCIe, or UART.We have added patches to optionally expose the Vexriscv debug bus over Ethernet at a given offset. This is an extremely convenient method of debugging, as it uses the same debugging interface we already use for other features such as our logic analyzer
litescope
.This series of patches includes a number of enhancements aimed at making the debugging process more reliable and efficient:
networkProtocol
to enable native Etherbone support. This protocol is described in slide 40 of https://accelconf.web.cern.ch/accelconf/icalepcs2011/talks/webhmult03_talk.pdf however theliteeth
project only supports a simplified subset (i.e. one read or write at a time). Depending on this protocol selection, the iverilog or etherbone protocol is used.mon reset halt
followed bycontinue
wouldn't actually reset the system.Comments are welcome.