search

SpinalHDL / openocd_riscv

Spen's Official OpenOCD Mirror
Other
45 stars 33 forks source link

Instructions in the README fail with "DEPRECATED!" warnings #13

Closed lindemer closed 3 years ago

lindemer commented 3 years ago

After building the repository, I attempt to run src/openocd -c "set VEXRISCV_YAML /home/<user>/VexRiscv/cpu0.yaml" -f tcl/target/vexriscv_sim.cfg. This produces the following output:

Open On-Chip Debugger 0.10.0+dev-01230-g33f5b081-dirty (2020-10-13-15:40)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
/home/<user>/VexRiscv/cpu0.yaml
DEPRECATED! use 'adapter driver' not 'interface'
Info : only one transport option; autoselect 'jtag'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter srst delay' not 'adapter_nsrst_delay'
Info : set servers polling period to 50ms
Error: target 'fpga_spinal.cpu0' init failed

I tried manually fixing the deprecated warnings by making the suggested replacements, but now it just fails with:

Info : only one transport option; autoselect 'jtag'
Info : set servers polling period to 50ms
Error: target 'fpga_spinal.cpu0' init failed

I can't do much with VexRiscv until I figure this out so help is greatly appreciated.

Dolu1990 commented 3 years ago

Hi, Those depreciated warnings are likely not the issue. Which simulation are you running ?

lindemer commented 3 years ago

I'm new to OpenOCD; could you clarify what you mean by which "simulation"? Right now I'm just trying to run the commands shown in the README to see if the installation worked.

Dolu1990 commented 3 years ago

Ahh, i mean, are you trying to connect to a physical target ? or a simulated one ?

lindemer commented 3 years ago

Simulated. Ideally I'd like to simulate VexRiscv and connect it GDB so I can work on a CPU plugin without flashing anything to my Arty FPGA.

I saw some other options like Renode and LiteX. Should I use one of those instead of OpenOCD?

Edit: I plan to run Zephyr which is supported by LiteX/VexRiscv.

Dolu1990 commented 3 years ago

The openocd commende itself will not run the simulation but try to connect to one that you should have already running into another terminal.

I saw some other options like Renode and LiteX. Should I use one of those instead of OpenOCD?

If you want raw CPU you have to use https://github.com/SpinalHDL/VexRiscv#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-and-verilator

Do you have the "make run DEBUG_PLUGIN_EXTERNAL=yes" command running into another shell ?

lindemer commented 3 years ago

Yes, I have make run DEBUG_PLUGIN_EXTERNAL=yes running in another shell but the OpenOCD command fails before executing so it doesn't seem to make a difference.

And yes, I'm following the instructions you linked.

Dolu1990 commented 3 years ago

I just tried the following using freshly pulled repo :

Shell 1 :

rawrr@rawrr:~/tmp/vexsim/VexRiscv$ sbt "runMain vexriscv.demo.GenFull"
[info] Loading global plugins from /home/rawrr/.sbt/1.0/plugins
[info] Loading settings for project vexriscv-build from plugins.sbt ...
[info] Loading project definition from /home/rawrr/tmp/vexsim/VexRiscv/project
[info] Updating ProjectRef(uri("file:/home/rawrr/tmp/vexsim/VexRiscv/project/"), "vexriscv-build")...
[info] Done updating.
[info] Loading settings for project root from build.sbt ...
[info] Set current project to VexRiscv (in build file:/home/rawrr/tmp/vexsim/VexRiscv/)
[info] Updating ...
[info] Done updating.
[warn] There may be incompatibilities among your library dependencies; run 'evicted' to see detailed eviction warnings.
[info] Compiling 74 Scala sources to /home/rawrr/tmp/vexsim/VexRiscv/target/scala-2.11/classes ...
[warn] there were 34 deprecation warnings; re-run with -deprecation for details
[warn] there were two feature warnings; re-run with -feature for details
[warn] two warnings found
[info] Done compiling.
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.google.protobuf.UnsafeUtil (file:/home/rawrr/.sbt/boot/scala-2.12.7/org.scala-sbt/sbt/1.2.7/protobuf-java-3.3.1.jar) to field java.nio.Buffer.address
WARNING: Please consider reporting this to the maintainers of com.google.protobuf.UnsafeUtil
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
[warn] Multiple main classes detected.  Run 'show discoveredMainClasses' to see the list
[info] Packaging /home/rawrr/tmp/vexsim/VexRiscv/target/scala-2.11/vexriscv_2.11-2.0.0.jar ...
[info] Done packaging.
[info] Running (fork) vexriscv.demo.GenFull 
[info] [Runtime] SpinalHDL v1.4.0    git head : ecb5a80b713566f417ea3ea061f9969e73770a7f
[info] [Runtime] JVM max memory : 8044.0MiB
[info] [Runtime] Current date : 2020.10.13 17:35:23
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 0.590 : Checks and transforms
[info] [Progress] at 0.855 : Generate Verilog
[info] [Warning] 116 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 0.978
[success] Total time: 18 s, completed Oct 13, 2020, 5:35:24 PM
rawrr@rawrr:~/tmp/vexsim/VexRiscv$ cd src/test/cpp/regression
rawrr@rawrr:~/tmp/vexsim/VexRiscv/src/test/cpp/regression$ make run DEBUG_PLUGIN_EXTERNAL=yes
cp ../../../../VexRiscv.v*.bin . | true
cp: cannot stat '../../../../VexRiscv.v*.bin': No such file or directory
verilator -cc  ../../../../VexRiscv.v  -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread  -CFLAGS -DREGRESSION_PATH='\".//\"' -CFLAGS -DIBUS_CACHED -CFLAGS -DDBUS_CACHED -CFLAGS -DREDO=10 -CFLAGS -pthread -CFLAGS -DTHREAD_COUNT=24 -CFLAGS -O3  -O3 -CFLAGS -DTIMER_INTERRUPT -CFLAGS -DEXTERNAL_INTERRUPT -CFLAGS -DDHRYSTONE -CFLAGS -DSTALL=1 -CFLAGS -DCSR -CFLAGS -DISA_TEST -CFLAGS -DMMU -CFLAGS -DMUL -CFLAGS -DDIV -CFLAGS -DDEBUG_PLUGIN -CFLAGS -DDEBUG_PLUGIN_STD -CFLAGS -DDEBUG_PLUGIN_EXTERNAL -CFLAGS -DTRACE_START=0 --gdbbt  -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
No stack.
make  -j24 -C obj_dir/ -f VVexRiscv.mk VVexRiscv
make[1]: Entering directory '/home/rawrr/tmp/vexsim/VexRiscv/src/test/cpp/regression/obj_dir'
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++11 -DREGRESSION_PATH=\".//\" -DIBUS_CACHED -DDBUS_CACHED -DREDO=10 -pthread -DTHREAD_COUNT=24 -O3 -DTIMER_INTERRUPT -DEXTERNAL_INTERRUPT -DDHRYSTONE -DSTALL=1 -DCSR -DISA_TEST -DMMU -DMUL -DDIV -DDEBUG_PLUGIN -DDEBUG_PLUGIN_STD -DDEBUG_PLUGIN_EXTERNAL -DTRACE_START=0  -std=gnu++14 -Os -c -o main.o ../main.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++11 -DREGRESSION_PATH=\".//\" -DIBUS_CACHED -DDBUS_CACHED -DREDO=10 -pthread -DTHREAD_COUNT=24 -O3 -DTIMER_INTERRUPT -DEXTERNAL_INTERRUPT -DDHRYSTONE -DSTALL=1 -DCSR -DISA_TEST -DMMU -DMUL -DDIV -DDEBUG_PLUGIN -DDEBUG_PLUGIN_STD -DDEBUG_PLUGIN_EXTERNAL -DTRACE_START=0  -std=gnu++14 -Os -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++11 -DREGRESSION_PATH=\".//\" -DIBUS_CACHED -DDBUS_CACHED -DREDO=10 -pthread -DTHREAD_COUNT=24 -O3 -DTIMER_INTERRUPT -DEXTERNAL_INTERRUPT -DDHRYSTONE -DSTALL=1 -DCSR -DISA_TEST -DMMU -DMUL -DDIV -DDEBUG_PLUGIN -DDEBUG_PLUGIN_STD -DDEBUG_PLUGIN_EXTERNAL -DTRACE_START=0  -std=gnu++14 -Os -c -o verilated_dpi.o /usr/local/share/verilator/include/verilated_dpi.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VVexRiscv.cpp VVexRiscv_VexRiscv.cpp VVexRiscv__Dpi.cpp VVexRiscv__Slow.cpp VVexRiscv_VexRiscv__Slow.cpp VVexRiscv__Syms.cpp > VVexRiscv__ALL.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++11 -DREGRESSION_PATH=\".//\" -DIBUS_CACHED -DDBUS_CACHED -DREDO=10 -pthread -DTHREAD_COUNT=24 -O3 -DTIMER_INTERRUPT -DEXTERNAL_INTERRUPT -DDHRYSTONE -DSTALL=1 -DCSR -DISA_TEST -DMMU -DMUL -DDIV -DDEBUG_PLUGIN -DDEBUG_PLUGIN_STD -DDEBUG_PLUGIN_EXTERNAL -DTRACE_START=0  -std=gnu++14 -Os -c -o VVexRiscv__ALL.o VVexRiscv__ALL.cpp
../main.cpp:1772:17: warning: ISO C++ forbids converting a string constant to ‘char*’ [-Wwrite-strings]
  char *target = "PROJECT EXECUTION SUCCESSFUL", *hit = target;
                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../main.cpp: In member function ‘virtual void ZephyrRegression::dutPutChar(char)’:
../main.cpp:1781:20: warning: NULL used in arithmetic [-Wpointer-arith]
         if(*hit == NULL) {
                    ^~~~
../main.cpp: In function ‘void loadHexImpl(std::__cxx11::string, Memory*)’:
../main.cpp:109:7: warning: ignoring return value of ‘size_t fread(void*, size_t, size_t, FILE*)’, declared with attribute warn_unused_result [-Wunused-result]
  fread(content, 1, size, fp);
  ~~~~~^~~~~~~~~~~~~~~~~~~~~~
../main.cpp: In function ‘void loadBinImpl(std::__cxx11::string, Memory*, uint32_t)’:
../main.cpp:164:7: warning: ignoring return value of ‘size_t fread(void*, size_t, size_t, FILE*)’, declared with attribute warn_unused_result [-Wunused-result]
  fread(content, 1, size, fp);
  ~~~~~^~~~~~~~~~~~~~~~~~~~~~
../main.cpp: In member function ‘virtual void Compliance::pass()’:
../main.cpp:2971:11: warning: ignoring return value of ‘size_t fread(void*, size_t, size_t, FILE*)’, declared with attribute warn_unused_result [-Wunused-result]
      fread(ref, 1, refSize, refFile);
      ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
../main.cpp:2983:11: warning: ignoring return value of ‘size_t fread(void*, size_t, size_t, FILE*)’, declared with attribute warn_unused_result [-Wunused-result]
      fread(log, 1, logSize, logFile);
      ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
../main.cpp: In member function ‘virtual void Dhrystone::pass()’:
../main.cpp:2916:11: warning: ignoring return value of ‘size_t fread(void*, size_t, size_t, FILE*)’, declared with attribute warn_unused_result [-Wunused-result]
      fread(ref, 1, refSize, refFile);
      ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
../main.cpp:2928:11: warning: ignoring return value of ‘size_t fread(void*, size_t, size_t, FILE*)’, declared with attribute warn_unused_result [-Wunused-result]
      fread(log, 1, logSize, logFile);
      ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
if test 0 -eq 0; then \
    ar -cr VVexRiscv__ALL.a VVexRiscv__ALL.o; \
    ranlib VVexRiscv__ALL.a; \
else \
    rm -f -f VVexRiscv__ALL__tmp.a; \
    ar -cr VVexRiscv__ALL__tmp.a  VVexRiscv__ALL.o; \
    ar -cqT VVexRiscv__ALL.a  VVexRiscv__ALL__tmp.a ; \
    printf "create VVexRiscv__ALL.a\n addlib VVexRiscv__ALL.a\n save\\n end" | ar -M; \
    rm -f -f VVexRiscv__ALL__tmp.a; \
fi
g++    main.o verilated.o verilated_dpi.o VVexRiscv__ALL.a   -pthread    -o VVexRiscv
make[1]: Leaving directory '/home/rawrr/tmp/vexsim/VexRiscv/src/test/cpp/regression/obj_dir'
./obj_dir/VVexRiscv
BOOT
CONNECTED

Shell 2 :

rawrr@rawrr:~/tmp/vexsim/openocd_riscv$ src/openocd -c "set VEXRISCV_YAML /home/rawrr/tmp/vexsim/VexRiscv/cpu0.yaml" -f tcl/target/vexriscv_sim.cfg
Open On-Chip Debugger 0.10.0+dev-01230-g33f5b081-dirty (2020-10-13-17:35)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
/home/rawrr/tmp/vexsim/VexRiscv/cpu0.yaml
DEPRECATED! use 'adapter driver' not 'interface'
Info : only one transport option; autoselect 'jtag'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter srst delay' not 'adapter_nsrst_delay'
Info : set servers polling period to 50ms
Info : clock speed 4000 kHz
Info : TAP fpga_spinal.bridge does not have valid IDCODE (idcode=0x0)
Info : TAP auto0.tap does not have valid IDCODE (idcode=0x80000000)
Info : TAP auto1.tap does not have valid IDCODE (idcode=0xc0000000)
Info : TAP auto2.tap does not have valid IDCODE (idcode=0xe0000000)
Info : TAP auto3.tap does not have valid IDCODE (idcode=0xf0000000)
Info : TAP auto4.tap does not have valid IDCODE (idcode=0xf8000000)
Info : TAP auto5.tap does not have valid IDCODE (idcode=0xfc000000)
Info : TAP auto6.tap does not have valid IDCODE (idcode=0xfe000000)
Info : TAP auto7.tap does not have valid IDCODE (idcode=0xff000000)
Info : TAP auto8.tap does not have valid IDCODE (idcode=0xff800000)
Info : TAP auto9.tap does not have valid IDCODE (idcode=0xffc00000)
Info : TAP auto10.tap does not have valid IDCODE (idcode=0xffe00000)
Info : TAP auto11.tap does not have valid IDCODE (idcode=0xfff00000)
Info : TAP auto12.tap does not have valid IDCODE (idcode=0xfff80000)
Info : TAP auto13.tap does not have valid IDCODE (idcode=0xfffc0000)
Info : TAP auto14.tap does not have valid IDCODE (idcode=0xfffe0000)
Info : TAP auto15.tap does not have valid IDCODE (idcode=0xffff0000)
Info : TAP auto16.tap does not have valid IDCODE (idcode=0xffff8000)
Info : TAP auto17.tap does not have valid IDCODE (idcode=0xffffc000)
Info : TAP auto18.tap does not have valid IDCODE (idcode=0xffffe000)
Info : TAP auto19.tap does not have valid IDCODE (idcode=0xfffff000)
Warn : Unexpected idcode after end of chain: 21 0xfffff800
Error: double-check your JTAG setup (interface, speed, ...)
Error: Trying to use configured scan chain anyway...
Error: fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : starting gdb server for fpga_spinal.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
requesting target halt and executing a soft reset
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'telnet' connection on tcp/4444

Shell 3 :

rawrr@rawrr:~/tmp/vexsim/openocd_riscv$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reg p
register p not found in current target

> reg pc
pc (/32): 0x80000000

> mdw 0x80000000 16
0x80000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 
0x80000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 

> mww 0x80000000 0x1234
> mdw 0x80000000 16    
0x80000000: 00001234 ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 
0x80000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff 

>

All seem good to me.

You are using that openocd fork right : ? https://github.com/SpinalHDL/openocd_riscv

lindemer commented 3 years ago

Thanks a lot @Dolu1990. I checked out all the repositories again and it worked as shown above. No idea what the issue was because I was running the same commands - maybe it was an library I updated at some point this afternoon.

Dolu1990 commented 3 years ago

Cool :)