error: array subscript has type 'char'

[acillatems]

Can't run "make" in openocd_riscv. Returns the following errors:

[Dolu1990]

Hi,

Which version of gcc do you have ?

[acillatems]

Hi,

My gcc version is: 12.2.0. I worked around this error by adding "(unsigned char)" in front of these lines.

But now there seems to be some problem with jimtcl. I get A LOT of undefined references during building and can't complete the build. Don't really know what causes these. Can it be that I am on too new version or something of sorts?

[Dolu1990]

Very likely it is GCC12.2.0 being more picky than before.

So i would say, it should work if you compile with a older GCC version, for instance, i have gcc (Ubuntu 10.1.0-2ubuntu1~18.04) 10.1.0

New GCC version have been constantly bringing up those new error, it is recurent

[acillatems]

I built it now with older version of GCC (10.3.0) but I ran in to new problems. When I try to launch openocd it gives me "The procedure entry point ftdi_tcioflush could not be located in the dynamic link library" and in eclipse: "OpenOCD failed with code (-1073741515)"

[Dolu1990]

Weird one, did you toke a fresh git clone before starting with this new gcc ?

[acillatems]

Yeah I started on fresh system altogether. I actually managed to get through that one. Not even sure how. I managed to get it somewhat working but now openocd logs:

I am using the Murax SoC and trying to get the hello_world on it using eclipse.

[acillatems]

I am using the murax with ram in it and Murax.cfg. And for JTAG configuration I have the digilent_jtag_hs3.cfg. And can't seem to get the hello_world.elf on the chip. All help would be greatly appreciated.

[Dolu1990]

Hi, So jtag tap 0x362d093 seems to indicate you use the jtag which is connected to the FPGA native jtag. By default Murax implement its own jtag tap in the FPGA logic (tap 0x10001fff). So two solutions, either you use connect a usb to jtag cable to the murax tap, either you need to modify Murax to use BSCANE2.

See https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag :)

[acillatems]

Hi, Thank you for the help! If I went with the first solution how would I be able to connect my usb to jtag cable to the murax tap?

I tried doing the steps in https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag but got the following error when trying to generate:

[error] Murax.scala:258:58: not enough arguments for method fromJtagInstructionCtrl: (jtagClockDomain: pinal.core.ClockDomain, jtagHeaderIgnoreWidth: Int)spinal.lib.com.jtag.JtagTapInstructionCtrl.

[error] Unspecified value parameter jtagHeaderIgnoreWidth.
[error]         jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
                                                                 ^

Edit: I was able to generate it with just putting the jtagHeaderIgnoreWidth value as "1". And was able to generate the bitstream and program it onto my device (the LEDs are blinking". But the same issues with my eclipse debugging session persists. Something is still very much wrong. I am sorry for all the hustle but I would like to get this working.

Also I suppose I won't be able to use the config files mentioned in that document so should I use the files I have been using so far? (interface\ftdi\digilent_jtag_hs3.cfg and target\murax.cfg). With these config files the logging is exactly the same as before the Murax customization.

[acillatems]

Ok I got it working! The issue seemed to be that I had used the "initialization commands" section to issue my own startup commands for gdp and therefore it received them twice I assume which caused the issues I was having after the last thing you suggested. Thank you for all the help so far!!

[Dolu1990]

Nice ^^ I think https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag is quite a old branch, probably you can use master branch