Error: 'JTAG scan chain interrogation failed: all zeroes' while launching OpenOCD for ztachip

[FaizanAhmad626]

Hey! I am using ztachip demo from this link: https://github.com/ztachip/ztachip

That demo is made for Arty A7 100T board but I am using Genesys 2 Kintex-7 Board (Part number: XC7K325T-2FFG900C). Here is the link to its reference manual: https://digilent.com/reference/programmable-logic/genesys-2/reference-manual I changed the hardware files to the best of my knowledge for my FPGA board. Now for the software part I followed the instructions given there but when I launched OpenOCD it gave the following error:

I think its because the configuration files being used in this demo are specified for Arty A7 board but my board is different. Here is the link to the configuration files being used in this demo: https://github.com/ztachip/ztachip/tree/master/tools/openocd

I do not know much about OpenOCD and these configuration files. Kindly can you help me out in this by guiding me how should I change these files for my board? Or do you have or provide any configuration files for my board so that I can run that demo. Or any material where I can get help from. I'll be really thankful to you.

[Dolu1990]

Hi,

I would say, first, to reduce the JTAG clock speed, 30MHz is realy a lot ^^ To be on the safe side, you can set it to 1Mhz (as a start) See https://github.com/ztachip/ztachip/blob/16d2dba447b7843f993b1aeb140f60e4e191f8a4/tools/openocd/usb_connect.cfg#L27

But looking at the genisis 2 board, how to you get the jtag on it ? Seems there is no FTDI on the board ?

[FaizanAhmad626]

Okay, I will change the clock speed. I'll also have to change it from the constraint file of ztachip. I'll share those lines.

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

I think these lines are responsible for debugging and I'll have to change the clock frequency in the first line from 300000000 to 1000000. Correct me if I'm wrong. I'm also having trouble understanding these lines.

And about JTAG. Genesys 2 board has JTAG connectivity.

I don't know about FTDI. How to check this?

[FaizanAhmad626]

In the reference manual of Genesys 2, it's written that JTAG supports 30 MHz frequency. Still 1 MHz should be used?

This is about Ftdi in Genesys 2 Kintex-7

[Dolu1990]

Ahhh i think that's not the ft232 which does the jtag, but the ft2232, which isn't in the schematic (blank page for some stupid reasons, if i didn't missed it)

Can you try the channel 1 ? https://github.com/ztachip/ztachip/blob/16d2dba447b7843f993b1aeb140f60e4e191f8a4/tools/openocd/usb_connect.cfg#L22

(ft2232 has 2 channels, 0 and 1)

[FaizanAhmad626]

Yes. The error is gone and the program loaded successfully. Thank you so much! :) Although now there is some other issue but the openocd is working fine now.