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SpinalHDL / openocd_riscv

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Error: cpuConfigFile ../VexRiscv/cpu0.yaml not found #36

Open BobMa0420 opened 1 year ago

BobMa0420 commented 1 year ago

Hi,I'm running VexRiscv on Sipeed TANG PRIMER 20K and I connect my board to the virtual machine via a usb jtag.

Then I'm trying to use openocd on my board with the command'src/openocd -c 'set VEXRISCV_YAML ../VexRiscv/cpu0.yaml' -f tcl/target/vexriscv_sim.cfg', the errors are as following.

Open On-Chip Debugger 0.11.0+dev-04033-g058dfa50d (2023-09-22-21:50) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html ../VexRiscv/cpu0.yaml Info : only one transport option; autoselect 'jtag' Info : set servers polling period to 50ms Error: cpuConfigFile ../VexRiscv/cpu0.yaml not found Error: target 'fpga_spinal.cpu0' init failed

I'm wondering how cpu0.yaml is generated or what is the location of it. Looing forward to your rely!

Dolu1990 commented 1 year ago

Hi, I'm not sure what configuration is exactly used, but in general cpu0.yaml look like : 

debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0}
iBus: !!vexriscv.BusReport
  flushInstructions: [4111, 19, 19, 19]
  info: !!vexriscv.CacheReport {bytePerLine: 64, size: 4096}
  kind: cached

one way to get it, is to delete the VexRiscvLitexSmpCluster* files in pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog

Run the litex geneartion

then get the cpu0.yaml file in pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/ext/VexRiscv