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Spritetm / hadbadge2019_fpgasoc

FPGA SoC code and application example for Hackaday Supercon 2019 badge
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PCM click fix causes violation of 48 MHz constraint #122

Closed ianjfrosst closed 5 years ago

ianjfrosst commented 5 years ago

With the changes in #118, making the soc/ errors with:

ERROR: Max frequency for clock                  '$glbnet$clk48m': 46.22 MHz (FAIL at 48.00 MHz)
Spritetm commented 5 years ago

Could depend on your see, can you change soc/Makefile to try a different one?

ianjfrosst commented 5 years ago

Tried and found a value that works. Should I make a PR for it?

Spritetm commented 5 years ago

You can if you want to, but there may not be much use, as the seed effects are consistent on one computer/install/... only. For instance, the current seed works for me. (pass at 51.79MHz)

ianjfrosst commented 5 years ago

Ah, I see. Though it might be deterministic. Well, that makes this issue irrelevant. Might make a PR making the seed value more clear for the FPGA docs.