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Spritetm / hadbadge2019_fpgasoc

FPGA SoC code and application example for Hackaday Supercon 2019 badge
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fix idle bug and formally verify #138

Closed mattvenn closed 4 years ago

mattvenn commented 4 years ago

I took a look at formally verifying the arbiter. I thought I found a bug (idle is never set to 1), but in fact it doesn't change the operation or throughput of the arbiter.

However, I have set it to 1 here, so that hold is released and idle becomes 1 as I think that is your intent. Might fix verilator warning too?

Spritetm commented 4 years ago

Whoah, I played with the idea of formally verifying bits and pieces of this design, but something about too few hours in the days before Supercon... Thanks!