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Spritetm / hadbadge2019_fpgasoc

FPGA SoC code and application example for Hackaday Supercon 2019 badge
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verilator doesn't operate clk24 #139

Open mattvenn opened 5 years ago

mattvenn commented 5 years ago

I'm looking at integrating new bits into the SOC, so I want to check they work. My design uses the 24 and 48 mhz clock, but only the 48 and 96 mhz clock is supplied by verilator. Is there a reason for this?

smunaut commented 5 years ago

Yeah, the 24 MHz clock wasn't used and each new clock increases sim time so we left it out so far.

mattvenn commented 5 years ago

So for example, in your fork that includes the HUB75 core, if I want to test that in simulation I will have to add the 24mhz clock to verilator (and fix those parameter issues)