search

StanfordAHA / CGRAFlow

Integration test for entire CGRA flow
BSD 3-Clause "New" or "Revised" License
12 stars 2 forks source link

Timing aware place and route, and retiming #78

Open priyanka-raina opened 5 years ago

Kuree commented 5 years ago

@priyanka-raina I'm very confused. I am not sure what kind of "timing aware" are you referring to.

Are you referring to multiple clock-domain? If that is the case, I can try to sketch out some simple clock-domain design on CGRA using Xilinx Ultrascale+ as an example. I also need to integrate that into Garnet since clock domain generation should be handled by the generator.

Or are you referring to critical path delay? In the largest design we have right now, time spent on SB and CB only takes about 20% of the critical path delay. Most of the time is on ALUs. I don't think timing aware PnR is going to help here.

Either way timing-aware PnR is a slew of research topics that requires months of work with a group of people, e.g., ISPD '17 timing-aware placement contest. I can definitely try it out, but not sure if the time frame is ideal.

priyanka-raina commented 5 years ago

I don't think this was intended to be finished by December, but something that came up, so I added it.

I think we meant critical path delay (I am guessing here) and reducing it by automatically adding pipeline registers to meet some desired clock frequency. We should be able to do it upstream if most of the time is in the ALUs. @mahorowitz ?