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StanfordAHA / CGRAMapper

CoreIR based mapping tool for CGRA
BSD 3-Clause "New" or "Revised" License
6 stars 4 forks source link

Incorrect mux logic #67

Closed Kuree closed 5 years ago

Kuree commented 6 years ago

Implementation of mux in the PE tile (see cgra_info.txt in CGRAGenerator repo):

<op sel='0x08' name='sel'>
    pe_out_res=op_d?op_a:op_b
    comp_res_p=(op_a+op_b) gte 2^16
</op>

It seems that CoreIR is assuming if selection bit bit0 == 0, outputs data0, which is consistent with most logic designs (I made that assumption too early on when debugging).

An easy and dirty fix would be swapping data.in.0 and data.in.1 in the mux pass, but it would be nice for the mapper to parse cgra_info.txt in the future so that it could generate netlists against different targets.

I can send a pull request to swap two operands if you want, but I'd like to do that based on your suggestion.

rdaly525 commented 6 years ago

@Kuree In the future, I agree it would be ideal to parse either cgra_info.txt or other collateral to generate the correct mappings.

You should easily be able to edit the cgralib_def.h file to implement this change.

Can you make sure that for our next chip, this bug gets fixed and the mux gets fixed? @rsetaluri, @leonardt

Note, sorry I have not been able to fix these issues. I have a paper deadline on Saturday which is consuming all my time.