Multiple producer synchronization

[jeffsetter]

When multiple producers connect to a single consumer, there needs to be some synchronization between the valid signals. There are issues when they are out-of-sync, as when they have a different valid signature.

[jeffsetter]

One solution is to make both have the same number of iterations.

Another solution is to connect a valid signal to the ren of the other producer.

[dillonhuff]

@jeffsetter maybe I'm misunderstanding, but isn't it the responsibility of the user to insert delays (using the fifo_depth scheduling directive) that synchronize the arrival times of data from different producers?

Is there a specific app where I could see an example of this problem?

[jeffsetter]

That is the case when linebuffers are used (which inherently must have some delay due to internal registers). My assumption for ROM is that there is zero delay. In fact, this is not correct, it takes a cycle, and so the thinking is the mapper will synchronize the arrival times with the actual timing.

[dillonhuff]

I think I understand. In the new CoreIR code generator I have added delay balancing for kernels with different latencies (for example because one uses a ROM and the other is all combinational logic).

Here is a test case for such a situation:

https://github.com/StanfordAHA/Halide-to-Hardware/blob/71f972a1cea4de10b13f64028416ab4ee899b70e/apps/hardware_benchmarks/tests/merged_unit_tests/test_main.cpp#L2544-L2597

Is this the kind of thing you are talking about or am I misunderstanding the problem?

[jeffsetter]

This is actually dynamic instead of just static latency between producers. For example, a producer might treat the edges differently from the other.