THE PROBLEM: Two of the forty-two center ICOVL alignment cells are surrounded by extra-large custom blockage regions. The blockage is causing a lot (thousands) of DRC errors. The blockage is inserted by a custom create_route_blockage command in top_garnet_staged.tcl, during the placement stage, just before it sources place.tcl. The two rectangles are big boxes around two of the ICOVL cells in the center array:
I "fixed" the problem by commenting out the create_route_blockage command and leaving the two cells with the same blockages as the other cells in the center array.
My questions:
why were the blockages inserted in the first place?
the ICOVL center array has moved a time or two since this command was written, I think; are the blockages even in the place where they were originally intended?
Also see:
git diff e3fd0c 3a7066 -- top_garnet_staged.tcl
#Fixes for ICOVL DRCs
- create_route_blockage -all {route cut} -rects {{2332 2684 2414 2733}{2331 3505 2414 3561}}
+ # - steveri 1912 omg what is this hack!!?? appears to be putting
+ # - extra-large blockage areas around just two of the 42 icovl blocks
+ # - but the area appears to be hard-wired and we've changed th icovl block
+ # - placement so who knows where they were supposed to be and why
+ # - as of now the blockage appears around blocks (1,0) and (1,13)
+ # - of the 2x21 array of center icovl blocks, where LL block is (0,0)
+ # - also note the blockage goes in *after* e.g. M1 stripes were built
+ # - so hella drc errors where they now overlap :(
+ # - i will file an issue
+ # create_route_blockage -all {route cut} -rects {{2332 2684 2414 2733}{2331 3505 2414 3561}}
set_db [get_db insts ifid_icovl*] .route_halo_size 4
set_db [get_db insts ifid_icovl*] .route_halo_bottom_layer M1
set_db [get_db insts ifid_icovl*] .route_halo_top_layer AP
Here's a screenshot showing the blockage around one of the two cells in the array...there is an identical blockage around the cell at the bottom right (not shown).
THE PROBLEM: Two of the forty-two center ICOVL alignment cells are surrounded by extra-large custom blockage regions. The blockage is causing a lot (thousands) of DRC errors. The blockage is inserted by a custom
create_route_blockage
command intop_garnet_staged.tcl
, during the placement stage, just before it sourcesplace.tcl
. The two rectangles are big boxes around two of the ICOVL cells in the center array:I "fixed" the problem by commenting out the
create_route_blockage
command and leaving the two cells with the same blockages as the other cells in the center array.My questions:
Also see:
git diff e3fd0c 3a7066 -- top_garnet_staged.tcl