Problems Parsing SystemVerilog

[alexcarsello]

Should add support for the following SystemVerilog features:

• [x] Signals of type Logic

• [ ] SystemVerilog interfaces in port declaration

• [ ] Pre/post-assignment operators (i.e. i++)

• [ ] "Enhanced for loop declaration"/Declaring loop variable inside for loop declaration.

[leonardt]

From what I can tell, logic is identical to reg. Inside the module definitions, it can be used in any way (we don't need to parse it since we're just wrapping the module). We do need to parse it in module interfaces (if we're importing the module). We could create a special Logic type instead of Bit in magma, or we could just map it to Bit.

Interfaces seem trickier. Again, if it's just used in the body of a module definition, then we can ignore it. However, if it's part of the declaration, we'll need to parse the interface declaration (should be similar to how we're parsing existing declarations). So this means we'll need to keep around a table of parsed interface declarations and add them to them to the interface of the current definition. Should be doable.