create_clock assertion check should only be for sequential circuits

StanfordAHA / pdq

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create_clock assertion check should only be for sequential circuits #16

Open rsetaluri opened 3 years ago

rsetaluri commented 3 years ago

https://github.com/StanfordAHA/pdq/blob/3acd3b70d1c10f12471f836f22fb07b932508001/flow/synopsys-dc-synthesis/configure.yml#L166

Since we allow comb. circuits in the flow, this assertion should be gated on the same flag as the constraints.

rsetaluri commented 3 years ago

@alexcarsello btw, I'm not sure the best way to do this. We could template the yaml file or somehow have that assertion itself (I'm assuming it gets interpolated into python somehow?) contain the switch.