The MM_CDR test is now part of the regression and passes.
The PRBS test now exercises both the built-in self test (internal PRBS generator) and the data path coming from the ADC.
Workarounds that were previously needed for the AC and LOOPBACK_RETIMER are removed.
JTAG-related I/O for all tests now exercises a path that was previously not covered (wiring from the raw JTAG interface to the various block-specific interfaces).
The GLITCH test now sweeps PI codes for each PI independently, and starts each PI at a realistic phase offset.
Details
To get the MM_CDR test passing, I did a number of things:
Set up the test so that it sends PRBS data through a channel model while looking for errors using the on-chip PRBS checker.
Set the bandwidth of the channel model so that FFE post-processing was not needed (and yet kept the bandwidth low enough that there is sufficient ISI for the baud-rate phase detector)
Increased Kp from 2 to 18. This effectively increased the loop bandwidth from ~150 Hz to ~10 MHz. For reference, the loop stops working at Kp=20. Note that Kp is the coefficient for the integral of phase error.
Disabled en_freq_est. (If we can run at a bandwidth of a few MHz, that should be fast enough to track spread-spectrum modulation occurring at ~30 kHz).
(This PR only modifies testing-related files)
Summary
MM_CDRtest is now part of the regression and passes.PRBStest now exercises both the built-in self test (internal PRBS generator) and the data path coming from the ADC.ACandLOOPBACK_RETIMERare removed.GLITCHtest now sweeps PI codes for each PI independently, and starts each PI at a realistic phase offset.Details
MM_CDRtest passing, I did a number of things:Kpfrom2to18. This effectively increased the loop bandwidth from ~150 Hz to ~10 MHz. For reference, the loop stops working atKp=20. Note thatKpis the coefficient for the integral of phase error.en_freq_est. (If we can run at a bandwidth of a few MHz, that should be fast enough to track spread-spectrum modulation occurring at ~30 kHz).