Get loopback emulation test working with mixed-signal emulation models

[sgherbst]

Summary

This PR incorporates auto-generated emulation models for channel dynamics, ADCs, and PIs, and includes a working loopback emulation test that exercises the MM-CDR, FFE, PRBS checker, and JTAG interface.

Details

I thought it would be good to highlight changes in the chip_src folder since those files are used in synthesis of the real chip, and therefore should have a higher level of scrutiny:

1. vlog/chip_src/analog_core/analog_core.sv:
   1. clk_div and clk_adc have special treatment for emulation, since clk_div is a bus of clock value signals (i.e. "regular" digital signals), while clk_adc is a true clock signal on the FPGA clock fabric (i.e. "special" digital signal). In CPU simulation and ASIC synthesis, there is no such a distinction.
   2. termination and biasgen are ifdef'd out for emulation, since Vivado doesn't do well with empty modules that are not black boxes (it is surprisingly hard to convince Vivado that we really want those modules to be empty)
2. vlog/chip_src/digital_core/digital_core.sv:
   1. For emulation, the freq_divider block that drives clk_avg is replaced with an assignment of clk_avg to "0", since the generated clock clk_avg was causing hold time issues. I think we should replace clk_avg with a clock enable signal in the future; this would be a good thing for both FPGA emulation and ASIC synthesis. Then we would only have one clock signal in the digital core, which is clk_adc.
   2. Vivado seems to have issues with slices of unpacked arrays (sets some signals to high-Z or X), so I used a generate statement to unpack the lower 16 values of adcout_unfolded into its own unpacked array, which is then passed to DSP and comparator blocks.
   3. weight_manager and dsp_backend instances have some constants replaced by parameters from packages to make it easier to rescale the FFE and MLSD blocks.
   4. I thought Vivado was not handling an assignment to a bus concatenation properly in the PRBS checker, so I moved those concatenations out of the PRBS checker instantiation. In reality, the issue was likely due to something else, but I think the code is at least as readable in this new form (if a bit more verbose).
3. vlog/chip_src/jtag/jtag.sv
   1. In one of the Markdown files, disable_product is set to a width of 10, but the width of ddbg_intf_i.disable_product may be 10 or 4 depending on whether we're running synthesis of the ASIC or FPGA emulator. It was not clear to me that was a simple way to get that particular constant into the Markdown file, so I updated the way those signals are assigned from the raw JTAG interface to avoid a width mismatch. (For FPGA emulation, the top 6 signals end up not being used for anything, but that is OK)
4. vlog/chip_src/weight_manager/wme_debug_intf.sv
   1. Some fixed values were replaced with parameters, as in the digital core. This made it easier to rescale the FFE and MLSD.

[codecov-commenter]

Codecov Report

Merging #104 into master will increase coverage by 0.41%. The diff coverage is 14.28%.

@@            Coverage Diff             @@
##           master     #104      +/-   ##
==========================================
+ Coverage   23.11%   23.53%   +0.41%     
==========================================
  Files          32       32              
  Lines        2059     2065       +6     
==========================================
+ Hits          476      486      +10     
+ Misses       1583     1579       -4     

Impacted Files	Coverage Δ
dragonphy/fpga_models/chan_core.py	0.00% <0.00%> (ø)
dragonphy/fpga_models/clk_delay_core.py	0.00% <0.00%> (ø)
dragonphy/fpga_models/osc_model_core.py	0.00% <0.00%> (ø)
dragonphy/fpga_models/rx_adc_core.py	0.00% <0.00%> (ø)
dragonphy/fpga_models/tx_core.py	0.00% <0.00%> (ø)
dragonphy/views.py	80.37% <ø> (+0.93%)	:arrow_up:
dragonphy/adapt_fir.py	25.00% <50.00%> (+9.61%)	:arrow_up:
dragonphy/anasymod.py	86.56% <60.00%> (-4.82%)	:arrow_down:
... and 1 more

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