This PR contains a variety of updates related to emulating the entire DragonPHY design (full FFE and MLSD lengths) on the ZC706 FPGA board. Since the regression server still uses ZC702 boards, which have fewer resources than ZC706, some logic is included to shrink the DragonPHY design for emulation regression tests only.
Details
experiments/cpu_emu_comparison now contains a CPU simulation for use in evaluating the emulator performance. This is based on the existing MM CDR + FFE + PRBS checker sim, but swaps in some simplified models for the ADC, PI, etc. so that the level of modeling the CPU simulation is close to that of the FPGA emulation (for a fairer comparison)
Results from various runs of this experiment are in experiments/cpu_emu_comparison/results.md
The dependency system is updated slightly so that the user can include a Path object in the override dictionary. This allows the user to specify the view name to use for a specific module (previous feature) or a direct path to the implementation (new feature).
conftest.py adds some new custom pytest options:
ffe_length: length of the FFE assumed for emulation. Should match value in config/system.yml. Perhaps a future PR could read the value from the YAML file to avoid duplicating it here.
emu_clk_freq: frequency to target when running the FPGA emulator. The ZC706 board can generally run faster than the ZC702 board, so it's useful to have this flexibility.
prbs_test_dur: how long to run the PRBS checker tests in emulation.
.buildkite/pipeline.yml is updated so that it re-writes the ffe_length and estimate_depth config values on the regression server, rather than maintaining two separate (but almost identical) config files for regression emulation vs. everything else.
codecov.yml is added to suppress some annoying default behavior from Codecov
This PR contains a variety of updates related to emulating the entire DragonPHY design (full FFE and MLSD lengths) on the ZC706 FPGA board. Since the regression server still uses ZC702 boards, which have fewer resources than ZC706, some logic is included to shrink the DragonPHY design for emulation regression tests only.
Details
experiments/cpu_emu_comparisonnow contains a CPU simulation for use in evaluating the emulator performance. This is based on the existing MM CDR + FFE + PRBS checker sim, but swaps in some simplified models for the ADC, PI, etc. so that the level of modeling the CPU simulation is close to that of the FPGA emulation (for a fairer comparison)experiments/cpu_emu_comparison/results.mdPathobject in theoverridedictionary. This allows the user to specify the view name to use for a specific module (previous feature) or a direct path to the implementation (new feature).conftest.pyadds some new custom pytest options:ffe_length: length of the FFE assumed for emulation. Should match value inconfig/system.yml. Perhaps a future PR could read the value from the YAML file to avoid duplicating it here.emu_clk_freq: frequency to target when running the FPGA emulator. The ZC706 board can generally run faster than the ZC702 board, so it's useful to have this flexibility.prbs_test_dur: how long to run the PRBS checker tests in emulation..buildkite/pipeline.ymlis updated so that it re-writes theffe_lengthandestimate_depthconfig values on the regression server, rather than maintaining two separate (but almost identical) config files for regression emulation vs. everything else.codecov.ymlis added to suppress some annoying default behavior from Codecov