At the moment, we generate the update signal used in adc_unfolding by sampling clk_avg with clk_retimer and then generating a one-cycle pulse when clk_avg transitions from 0 to 1. The issue is that clk_avg is generated with a freq_divider module that creates several generated clocks. For FPGA synthesis, at least, this causes some timing issues. By removing the freq_divider in digital_core and directly generating the update signal, we will get back to having only one clock signal in digital_core, which is clk_adc. This will resolve the FPGA synthesis issue, while also simplifying ASIC synthesis.
At the moment, we generate the
updatesignal used inadc_unfoldingby samplingclk_avgwithclk_retimerand then generating a one-cycle pulse whenclk_avgtransitions from0to1. The issue is thatclk_avgis generated with afreq_dividermodule that creates several generated clocks. For FPGA synthesis, at least, this causes some timing issues. By removing thefreq_dividerindigital_coreand directly generating theupdatesignal, we will get back to having only one clock signal indigital_core, which isclk_adc. This will resolve the FPGA synthesis issue, while also simplifying ASIC synthesis.