This PR adds a second, higher-level approach for modeling analog effects in DragonPHY. Rather than modeling the ADC and PI slices in analog_core directly, analog_core itself is replaced by a synthesizable behavioral model. This allows the emulator to do more parallel processing of the analog dynamics, ultimately pushing the emulator throughput from 5 Mb/s to 80 Mb/s (on a ZC706 board).
Details
The previous emulation modeling style is still available; tests/fpga_system_tests/emu uses that approach while tests/fpga_system_test/emu_macro uses the newer, higher-performance style. Both are tested to some extent within the DragonPHY regression flow, since there are interesting use cases for both approaches.
The basic unit of modeling for this new approach is called analog_slice. It is essentially a macro-model for a PI+ADC, where the PI control code sets the sample time for the ADC, and the ADC slice computes the sampled voltage based on the history of bits transmitted through the link and the analog dynamics of the channel. Each analog_slice takes several cycles to compute the sampled voltage, since it operates on the history of previous bits in chunks (8 bits per chunk and 4 chunks total). This is necessary to fit within the DSP resources available on the FPGA.
Added new pytest command-line options simulator_name and fpga_sim_ctrl
For simulator_name, it can be iverilog, icarus, xrun, ncsim, or vivado. Due to a discrepancy between how fault and anasymod refer to simulators, {iverilog, ncsim, vivado} should be used with fault-based tests, while anasymod-based tests should use {icarus, xrun, vivado}. This command-line argument replaces the SIMULATOR_NAME variable that was in many existing tests. I went through and updated those tests accordingly.
For fpga_sim_ctrl, it can be either UART_ZYNQ (default, recommended) or VIVADO_VIO. The VIVADO_VIO option is basically just for comparison purposes because it is so much slower than UART_ZYNQ (at least 1000x slower).
Added a new experiment for FPGA emulation called experiments/jtag_comparison. This experiment looks at 5 different ways to generating a JTAG stimulus for the DUT.
Summary
This PR adds a second, higher-level approach for modeling analog effects in DragonPHY. Rather than modeling the ADC and PI slices in
analog_coredirectly,analog_coreitself is replaced by a synthesizable behavioral model. This allows the emulator to do more parallel processing of the analog dynamics, ultimately pushing the emulator throughput from 5 Mb/s to 80 Mb/s (on a ZC706 board).Details
tests/fpga_system_tests/emuuses that approach whiletests/fpga_system_test/emu_macrouses the newer, higher-performance style. Both are tested to some extent within the DragonPHY regression flow, since there are interesting use cases for both approaches.analog_slice. It is essentially a macro-model for a PI+ADC, where the PI control code sets the sample time for the ADC, and the ADC slice computes the sampled voltage based on the history of bits transmitted through the link and the analog dynamics of the channel. Eachanalog_slicetakes several cycles to compute the sampled voltage, since it operates on the history of previous bits in chunks (8 bits per chunk and 4 chunks total). This is necessary to fit within the DSP resources available on the FPGA.pytestcommand-line optionssimulator_nameandfpga_sim_ctrlsimulator_name, it can beiverilog,icarus,xrun,ncsim, orvivado. Due to a discrepancy between howfaultandanasymodrefer to simulators,{iverilog, ncsim, vivado}should be used withfault-based tests, whileanasymod-based tests should use{icarus, xrun, vivado}. This command-line argument replaces theSIMULATOR_NAMEvariable that was in many existing tests. I went through and updated those tests accordingly.fpga_sim_ctrl, it can be eitherUART_ZYNQ(default, recommended) orVIVADO_VIO. TheVIVADO_VIOoption is basically just for comparison purposes because it is so much slower thanUART_ZYNQ(at least 1000x slower).experiments/jtag_comparison. This experiment looks at 5 different ways to generating a JTAG stimulus for the DUT.