This PR leverages new features in msdsl and svreal to model channel dynamics in a way that can be updated at runtime, without requiring the bitstream to be rebuilt. The feature has been added to both high-level and low-level emulator architectures. Emulator throughput was not affected by this change, but it was interesting to note that BRAM utilization is up while LUT utilization is down. This suggests that Vivado synthesis had been using LUTs to implement some synchronous ROMs in the previous implementations of channel dynamics.
Here's an example of what updating the step response function at runtime looks like from a user perspective:
placeholder = PlaceholderFunction(...) # defines fixed-point formatting of piecewise-polynomial coefficients
chan_func = ... # can use a regular Python function here
coeffs_bin = placeholder.get_coeffs_bin_fmt(chan_func)
coeff_tuples = list(zip(*coeffs_bin))
update_chan(coeff_tuples) # transmits coefficients to FPGA over USB-UART
Details
As usual, most of the changes in the PR are in the testing infrastructure; the updates to the models themselves (analog_slice and chan_core) are about 25 lines each.
The updatable functions can be configured via config/fpga/analog_slice_cfg.yml (high-level architecture) and config/fpga/chan.yml (low-level architecture)
New pytest options --chan_tau and --chan_delay allow the user to conveniently specify the time constant and delay for the channel, assuming an exponential step response. However, the user can provide their own function if an exponential step response is not sufficient, without having to rebuild the bitstream.
Summary
This PR leverages new features in
msdsl
andsvreal
to model channel dynamics in a way that can be updated at runtime, without requiring the bitstream to be rebuilt. The feature has been added to both high-level and low-level emulator architectures. Emulator throughput was not affected by this change, but it was interesting to note that BRAM utilization is up while LUT utilization is down. This suggests that Vivado synthesis had been using LUTs to implement some synchronous ROMs in the previous implementations of channel dynamics.Here's an example of what updating the step response function at runtime looks like from a user perspective:
Details
analog_slice
andchan_core
) are about 25 lines each.config/fpga/analog_slice_cfg.yml
(high-level architecture) andconfig/fpga/chan.yml
(low-level architecture)pytest
options--chan_tau
and--chan_delay
allow the user to conveniently specify the time constant and delay for the channel, assuming an exponential step response. However, the user can provide their own function if an exponential step response is not sufficient, without having to rebuild the bitstream.