This PR adds an option for emulating the design using a floating-point representation (Berkeley HardFloat) instead of a fixed-point representation, making use of new features in msdsl and svreal. With this update, I was able to gather a key piece of data regarding floating- vs. fixed-point: for the high-level emulator architecture on the ZC706 board, the emulator is about 17x slower when using floating-point as compared to fixed-point. This is for two reasons:
The floating-point operators are about 3x slower than their fixed-point equivalents
The floating-point operators are more resource intensive, and as such required a 5.7x reduction in parallelism of the emulator calculations to fit within the FPGA resources.
Details
Changing num_chunks and chunk_width in config/fpga/analog_slice_cfg.yml actually works now. In other words, you are free to adjust the parallelism of the high-level emulator without having to update the code in a bunch of places.
The serial port for the emulator is now detected automatically, making use of a new feature from anasymod
Added code to generate an EDIF file for the TAP core, if needed for emulation
Updated experimental results file (might want to move this to the project wiki at some point)
Summary
This PR adds an option for emulating the design using a floating-point representation (Berkeley HardFloat) instead of a fixed-point representation, making use of new features in msdsl and svreal. With this update, I was able to gather a key piece of data regarding floating- vs. fixed-point: for the high-level emulator architecture on the ZC706 board, the emulator is about 17x slower when using floating-point as compared to fixed-point. This is for two reasons:
Details
num_chunksandchunk_widthinconfig/fpga/analog_slice_cfg.ymlactually works now. In other words, you are free to adjust the parallelism of the high-level emulator without having to update the code in a bunch of places.