The main goal of this PR is to get simulation and emulation BER estimates to match better. With the updates included here, the estimates are now match to within 7.5% or better at BER levels ranging from 1e-2 to 1e-4. For BERs between 1e-5 and 1e-6, I have looked at the low-level and high-level emulators and found that they match to within the same tolerance.
This PR is large mainly because it includes a lot a experimental code and results in the experiments folder. Might be interesting to think about if there is a better home for that code. I do like keeping experiments under revision control, though, because it makes it easier to replicate results.
Details
There are several key updates to improve BER matching, both to the emulator implementations and the simulation baseline itself:
Emulation
Switch from using an LFSR for random integer generation to using a Linear Congruential Generator (LCG); this is what the Verilog spec calls for. While a Mersenne Twister would be "more random", it produces quite different results. For now, it's simply left up to the user whether they want to use an LCG or Mersenne.
Use a pseudo-logarithmic compression in implementing the inverse CDF of a Gaussian. This ends up focusing more PWL segments at parts of the function near zero, which are extremely sharp and nonlinear.
For the low-level emulator, fix the PI model so that it can handle delays that are slightly greater than one period (due to jitter).
For the high-level emulator, implement two details that are automatically covered by the low-level emulator and simulation baseline:
Clamp jittery PI delays to be nonnegative
Fix handling of PI delays that end up going beyond the clk_adc sampling point.
For both emulators, make the PRBS generator use the same equation as the mLingua PRBS21 module. For the high-level case, this requires seeding the parallel PRBS generators in a certain way.
For both emulators, fix the TX and RX Vref levels to match simulation.
Simulation
Fix two bugs in the baseline ADC model: noise was being added to the magnitude, rather than to the signal, and the ADC was rounding, instead of taking the floor.
Use tighter etol value for mLingua
Use a fast bit -> PWL transition in the TX driver so that the channel response is dominated by the first order pole.
Make the 8 GHz DragonPHY input clock derived from the 16 GHz TX clock to avoid simulator drift
More details follow as comments in the code. It may be more convenient to view them by clicking on the "Files changed" tab, so that you can see the comments in context.
Summary
The main goal of this PR is to get simulation and emulation BER estimates to match better. With the updates included here, the estimates are now match to within 7.5% or better at BER levels ranging from 1e-2 to 1e-4. For BERs between 1e-5 and 1e-6, I have looked at the low-level and high-level emulators and found that they match to within the same tolerance.
This PR is large mainly because it includes a lot a experimental code and results in the
experimentsfolder. Might be interesting to think about if there is a better home for that code. I do like keeping experiments under revision control, though, because it makes it easier to replicate results.Details
There are several key updates to improve BER matching, both to the emulator implementations and the simulation baseline itself:
clk_adcsampling point.etolvalue for mLinguaMore details follow as comments in the code. It may be more convenient to view them by clicking on the "Files changed" tab, so that you can see the comments in context.