Move retimer into analog core

[sgherbst]

Summary

As discussed at yesterday's meeting, this PR moves the retimer function into the analog core. The retimer is split up among all of the ADC slices, but its implementation is unchanged. I made the necessary updates to the analog core, digital core, JTAG registers, and QTM generator to support this. The meaning of retimer_mux_ctrl_1 and retimer_mux_ctrl_2 is kept the same as before (see graphic below).

Note: this PR is independent from the other two open PRs, #116 and #114. All of those PRs can be merged in any order.

Details

1. For the mux control registers, bit k maps to ADC slice (k/4)+((k%4)*4). This is the same as before, so the values of the mux control registers did not have be changed in existing tests.
2. For completeness, there are new registers retimer_mux_ctrl_1_rep and retimer_mux_ctrl_2_rep for the replica ADCs. Probably not necessary, but since we now have those control knobs, we might as well let the user adjust them.
3. There is still a block in the digital core where ti_adc_retimer_v2 used to be, but it is now called ti_adc_reorder, and just does the reordering. This new module has its own block-level test.
4. The QTM model for the analog core is simplified since all ADC outputs are registered to clk_adc (no longer have to compute the delays on a per-slice basis). Similarly, in the top-level timing constraints, it is no longer necessary to specify particular values for the mux control registers in order to close timing.

For more details, see "Files changed", where I added a bunch of comments.

[sgherbst]

Note: we might want to consider rearranging the logic in the retimer to avoid combo logic on the output. But for now I kept the implementation exactly the same as before.