Through some experimentation, I found that the analog_core quick timing model (QTM) was not being used in synthesis. This PR fixes that problem with a couple of updates to the synthesis flow.
Details
There were several issues causing this situation:
An empty Verilog stub for analog_core was being included in addition to the analog_core QTM. This was masking problems with the QTM, because the synthesis tool failed to link to the analog_core QTM, but could fall back to the Verilog stub, apparently without raising a warning. I removed the stub from the source list to prevent this from happening in the future (dragonphy/views.py).
The names of pins in the analog_core QTM used an underscore instead of a period to separate the interface name from the signal name. I believe this was because we had previously tried to have the synthesis tool flatten interfaces into signal names with an underscore. However, this does not appear to be necessary, and seems to have caused more problems than it solved. The takeaway is that the QTM should refer to signals in an interface using a period, just like they would be referenced in ordinary SystemVerilog code.
When the Verilog design is read in, it is not necessary to use change_names or rename_design to modify the names of pins on the analog_core interface (designs/dragonphy_top/rtl/gen_tcl.py).
Now that change_names was removed from the design read-in procedure, timing constraints that referred to interfaces using an underscore also had to be changed back to a period.
Verification
I tested this change in two ways:
I made the timing arc very long for ADC data in the analog_core QTM (99% of the clock period). I then verified that this change made the design fail timing.
I intentionally added a typo to the name of a pin in the analog_core QTM and verified that this caused the synthesis flow to raise an error that indicated a naming mismatch.
Summary
Through some experimentation, I found that the
analog_corequick timing model (QTM) was not being used in synthesis. This PR fixes that problem with a couple of updates to the synthesis flow.Details
There were several issues causing this situation:
analog_corewas being included in addition to theanalog_coreQTM. This was masking problems with the QTM, because the synthesis tool failed to link to theanalog_coreQTM, but could fall back to the Verilog stub, apparently without raising a warning. I removed the stub from the source list to prevent this from happening in the future (dragonphy/views.py).analog_coreQTM used an underscore instead of a period to separate the interface name from the signal name. I believe this was because we had previously tried to have the synthesis tool flatten interfaces into signal names with an underscore. However, this does not appear to be necessary, and seems to have caused more problems than it solved. The takeaway is that the QTM should refer to signals in an interface using a period, just like they would be referenced in ordinary SystemVerilog code.change_namesorrename_designto modify the names of pins on theanalog_coreinterface (designs/dragonphy_top/rtl/gen_tcl.py).change_nameswas removed from the design read-in procedure, timing constraints that referred to interfaces using an underscore also had to be changed back to a period.Verification
I tested this change in two ways:
analog_coreQTM (99% of the clock period). I then verified that this change made the design fail timing.analog_coreQTM and verified that this caused the synthesis flow to raise an error that indicated a naming mismatch.