Closed sgherbst closed 3 years ago
I will update this branch to remove the misc_ctrl_bits
register, now that the allowed number of JTAG registers has been increased.
It looks a new test "loopback_sram_int" is added and cpu regression fails in the test. Can you add 30ps of delay to the input clocks (ext_clk) in "/cpu_system_tests/loopback_sram_int/test.sv"?
Thanks @sjkim85 for catching that -- I just updated the code. The other test I added is mm_cdr_slew
, which is slightly modified from mm_cdr
-- did you need to make any changes to that test for the analog_core_updates
branch?
@sgherbst , I think I don't need to make change to that test. After this PR (#126) is merged to master I will push analog_core_update again with adding QTM of PI and slight change of V2T (which are not relevant to the new tests you added)
Summary
This PR addresses three open issues:
Details
misc_ctrl_bits
. There's plenty of extra room in this register for future expansion -- only 5 of the bits are currently being used.misc_ctrl_bits[2]
to1
(to enable the feature), then set/clearmisc_ctrl_bits[3]
to toggle the internaldump_start
pin.misc_ctrl_bits[3]
to1
to enable the feature. The clamp amount can be adjusted, if needed, via a 32-bit signed register calledcdr_clamp_amt
. It defaults to +/-1, though, so you may not need to change it.experiments/pi_local_encoder
.