This PR instantiates the transmitter at the top level of DragonPHY and wires it up. This includes additional logic in the digital core to set the PI codes for the TX, as well as a block that can generate four kinds of TX data patterns:
PRBS: intended for a loopback test
Pulse generator: intended for channel characterization. The width of the pulse can be 1-16 UI.
Constant output: intended for DC characterization of the TX output buffer.
Square wave generator, adjustable from 8 GHz down to about 8 kHz. Intended for debugging the TX output bandwidth.
Not included in this PR
System-level test of the TX. This will be added after the block-level test of the TX is complete.
Self-checking capability in the block-level test of the TX data generator. Will be added in a future PR. (For now the test passes if the simulation completes without errors.)
Other details
Added JTAG registers for the TX and its data generator.
Did a preliminary update of the synthesis constraints for the transmitter, but didn't add any constraints within the transmitter itself for the various divided clocks. I'll need input from @CansWang on that, but it can wait until the next PR, since the synthesis test is passing.
Updated mflowgen steps having to do with the phase interpolator and input divider, which are instantiated as black boxes by the transmitter.
Wrapped default_nettype none / default_nettype wire around TX design sources to help catch typos (this will cause the simulator / synthesis tool to error out when an implicit wire is detected). I had to update some IOs to input wire logic or output wire logic to be compatible with this change.
Moved fppi to the vlog/tb folder since it is not a design source.
Removed md/sram_intf_md (note that it ends with _md, not .md). It looks like this file is obsolete.
Summary
This PR instantiates the transmitter at the top level of DragonPHY and wires it up. This includes additional logic in the digital core to set the PI codes for the TX, as well as a block that can generate four kinds of TX data patterns:
Not included in this PR
Other details
default_nettype none/default_nettype wirearound TX design sources to help catch typos (this will cause the simulator / synthesis tool to error out when an implicit wire is detected). I had to update some IOs toinput wire logicoroutput wire logicto be compatible with this change.fppito thevlog/tbfolder since it is not a design source.md/sram_intf_md(note that it ends with_md, not.md). It looks like this file is obsolete.