search

StanfordVLSI / dragonphy2

Open Source PHY v2
Apache License 2.0
21 stars 3 forks source link

Add output buffer (and termination?) for TX #137

Closed sgherbst closed 3 years ago

sgherbst commented 3 years ago

Just wanted to log this issue here so that we can keep track of it. I'm assigning @CansWang since he is the TX designer, and it would be great to hear thoughts from @sjkim85 as well because he designed the differential output buffer used in the digital core.

sjkim85 commented 3 years ago

The output buffer in DCORE is just inverter chain for monitoring purpose and its output impedance is not matched at all. I thought our TX contains output driver stage to drive channel. Am I right Can?

-Sung-Jin

Sent via the Samsung Galaxy S8+, an AT&T 5G Evolution capable smartphone Android용 Outlookhttps://aka.ms/ghei36 다운로드

From: Steven Herbst notifications@github.com Sent: Saturday, October 24, 2020 12:45:34 PM To: StanfordVLSI/dragonphy2 dragonphy2@noreply.github.com Cc: Sung-Jin Kim sjkim85@stanford.edu; Mention mention@noreply.github.com Subject: [StanfordVLSI/dragonphy2] Add output buffer (and termination?) for TX (#137)

Just wanted to log this issue here so that we can keep track of it. I'm assigning @CansWanghttps://github.com/CansWang since he is the TX designer, and it would be great to hear thoughts from @sjkim85https://github.com/sjkim85 as well because he designed the differential output buffer used in the digital core.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHubhttps://github.com/StanfordVLSI/dragonphy2/issues/137, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AGWDJIT7I5M76VL3YVUJFDLSMMVF5ANCNFSM4S5ZR6GQ.

CansWang commented 3 years ago

The output buffer in DCORE is just inverter chain for monitoring purpose and its output impedance is not matched at all. I thought our TX contains output driver stage to drive channel. Am I right Can? … -Sung-Jin Sent via the Samsung Galaxy S8+, an AT&T 5G Evolution capable smartphone Android용 Outlookhttps://aka.ms/ghei36 다운로드 ____ From: Steven Herbst notifications@github.com Sent: Saturday, October 24, 2020 12:45:34 PM To: StanfordVLSI/dragonphy2 dragonphy2@noreply.github.com Cc: Sung-Jin Kim sjkim85@stanford.edu; Mention mention@noreply.github.com Subject: [StanfordVLSI/dragonphy2] Add output buffer (and termination?) for TX (#137) Just wanted to log this issue here so that we can keep track of it. I'm assigning @CansWanghttps://github.com/CansWang since he is the TX designer, and it would be great to hear thoughts from @sjkim85https://github.com/sjkim85 as well because he designed the differential output buffer used in the digital core. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub<#137>, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AGWDJIT7I5M76VL3YVUJFDLSMMVF5ANCNFSM4S5ZR6GQ.

The Tx output stage needs to be designed together with the termination and integrate into tx_top.sv. There are essentially two ways of designing it (?)

since we want to minimize the delay and number of stages, also make the on resistance + termination to be closer to 50 ohm (single ended) 1) design this in virtuoso 2) synthesize it, (I am not familiar with this method), but we should be able to specify the fanout (parasitic at the output) and unit size (determined by sheet resistance of diffusion)

Correct me if anything doesn't make sense to you, thanks!

sgherbst commented 3 years ago

Closing as this was resolved in #146