This PR updates the timing constraints for signals related to the TX. It also removes a non-synthesizable initial block from div_b2.
Details
create_clock is used to declare four 4 GHz clocks at the outputs of the PIs in the TX. They are given phase shifts of 0, 90, 180, and 270 degrees.
There are four clock dividers in the TX, and create_generated_clock is used to describe their behaviors.
The setup/hold clock uncertainty for all of these clocks (4 GHz, 2 GHz, and 1 GHz) are set to a few percent their period: The 1 GHz clocks are given an uncertainty of 30 ps, the 2 GHz clocks are given an uncertainty of 20 ps, and the 4 GHz clocks are given an uncertainty of 10 ps.
The TX clocks are grouped together with set_clock_groups. This means that clock domain crossings between the various TX clocks are analyzed, but crossings to other clocks (clk_adc, clk_jtag, etc.) are not.
The maximum transition of TX clocks is set to 10% of their periods: 100ps for 1 GHz clocks, 50ps for 2 GHz clocks, and 25ps for 4 GHz clocks.
create_clock is not longer used for debug clock signals that are monitored with the output_buffer. Those nets are now treated as regular signals, but given a stricter-than-default max_transition of 25ps (i.e., 10% of the 4 GHz period)
Summary
This PR updates the timing constraints for signals related to the TX. It also removes a non-synthesizable
initialblock fromdiv_b2.Details
create_clockis used to declare four 4 GHz clocks at the outputs of the PIs in the TX. They are given phase shifts of 0, 90, 180, and 270 degrees.create_generated_clockis used to describe their behaviors.set_clock_groups. This means that clock domain crossings between the various TX clocks are analyzed, but crossings to other clocks (clk_adc,clk_jtag, etc.) are not.create_clockis not longer used for debug clock signals that are monitored with theoutput_buffer. Those nets are now treated as regular signals, but given a stricter-than-defaultmax_transitionof 25ps (i.e., 10% of the 4 GHz period)