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StanfordVLSI / dragonphy2

Open Source PHY v2
Apache License 2.0
21 stars 3 forks source link

output_buf module create #146

Closed CansWang closed 3 years ago

CansWang commented 3 years ago

Just create the output buffer module.

1) Dividers div_b2 that were originally in qr_4t1 and hr_16t4 are moved to tx_top. 2) Interface added for output buffer slice number control. Control bits are 8-bit wide and independent between positive and negative output.

At this point, the buildkite check will definitely fail because the output buffer is a direct instantiation of tsmcN16 std cell logic gate. Please ignore this temporary. @sgherbst

sgherbst commented 3 years ago

@CansWang one last comment -- it looks like this branch is out-of-date with the master branch; would you mind updating it? Thanks!