Analog core2

[sjkim85]

[summary of PR] 1) Syn/Pnr flow for “phase_interpolator”, ”biasgen”, ”input_divider” are added. (now all blocks in the acore is uploaded) 2) biasgen.sv and input_divider.sv netlists are updated to be fully synthesizable 3) 2 pins are added to the input_divider.sv (in_mdll/sel_clk_source) and 1 pin is added to analog_core.sv (mdll_clk) to take an additional clock from MDLL. (associated jtag_intf/md is updated) 4) bin2thm_4b.sv and bin2thm_5b.sv are merged into bin2thm.sv 5) stochastic_adc_PR_dont_touch.tcl and phase_interpolator_dont_touch.tcl are added and merged into pnr flow. 6) gate_size_test.sv is upgraded for better gate-size mapping 7) The issue about mismatch between syn_constraints and sdc is resolved (by syn.sh) 8) Several generic gates requiring proper size are added to /new_chip_src/analog_core (inv_bld_x_fixed.sv, mux_bld_fixed.sv, n_and_arb_fixed.sv, inv_arb_fixed.sv, mux4_fixed etc..) 9) Main scripts of the flow (syn.sh/pnr.sh/run_all_templete/Makefile_templete) are updated for more automation. 10) Syn/PnR coefficients are not fully tuned yet and the PnR result of PI/ADC has DRC errors. 11) Syn/PnR flow of analog_core.sv is not uploaded yet (under construction). 12) Syn constraints of butterphy_top is uploaded.

[codecov-io]

Codecov Report

Merging #2 into master will not change coverage. The diff coverage is n/a.

@@           Coverage Diff           @@
##           master       #2   +/-   ##
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  Coverage   21.60%   21.60%           
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  Files          31       31           
  Lines        1754     1754           
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  Hits          379      379           
  Misses       1375     1375           

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