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StanfordVLSI / dragonphy2

Open Source PHY v2
Apache License 2.0
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Check polarity of bypass_inbuf_div #53

Closed sgherbst closed 4 years ago

sgherbst commented 4 years ago

From the behavioral model of the input buffer (transcribed from a schematic), It looks like bypass_inbuf_div = 0 means that the input buffer divider should be bypassed, which seems inverted to me. I'm not sure if this is a model issue or present in the implementation as well, so it is worth checking this polarity as well as the default register value. This should be clarified somewhat by the completion of issue StanfordVLSI/dragonphy#55, which should eliminate behavioral models for input and output buffers.

sjkim85 commented 4 years ago

It seems confusing to me as well but what I intended it like this. There are two cascaded dividers in the input buffer : div2 (default) and sync_divider (can be controlled and disabled) When bypass_inbuf_div =1, the sync_divider is bypassed and output is directly connected to output of div2. Could you check again If I am right?

sgherbst commented 4 years ago

That's what I would have thought the behavior is, so it may just be an error in my model. Let's keep this issue open until StanfordVLSI/dragonphy#55 is completed, then we can revisit to see if the behavioral persists.

sgherbst commented 4 years ago

This issue was resolved when we switched to modeling the input / output dividers at gate level