Closed sgherbst closed 4 years ago
the JTAG reset pin is controlled by the JTAG controller.
-Zach
On May 1, 2020, at 9:42 AM, Steven Herbst notifications@github.com wrote:
During a meeting a few days ago, we defined the reset sequence as:
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Sorry, to clarify I mean when this should happen, rather than how. It definitely needs to happen before step 2 (since that involves JTAG communication), so I think my question can be simplified to "which should be de-asserted first, ext_rstb
or phy_trst_n
"
It happens after ext_rstb is de-asserted. I can double check the logic but I believe the ext_rstb acts as a standard reset inside the JTAG and the JTAG's trst_n's primary function is to reset JTAG state machine into a known state.
-Zach
From: Steven Herbst notifications@github.com Sent: Friday, May 1, 2020 10:26 AM To: StanfordVLSI/dragonphy2 dragonphy2@noreply.github.com Cc: Zachary Alexander Myers zamyers@stanford.edu; Comment comment@noreply.github.com Subject: Re: [StanfordVLSI/dragonphy2] Where does JTAG fit into the reset sequence? (#60)
Sorry, to clarify I mean when this should happen, rather than how. It definitely needs to happen before step 2 (since that involves JTAG communication), so I think my question can be simplified to "which should be de-asserted first, ext_rstb or phy_trst_n"
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Great, thanks. In that case I'll update the reset sequence to
ext_rstb
phy_trst_n
int_rstb
(over JTAG)en_inbuf
en_gf
en_v2t
During a meeting a few days ago, we defined the reset sequence as:
ext_rstb
int_rstb
(over JTAG)en_inbuf
en_gf
en_v2t
But I realized this doesn't include the JTAG reset pin,
phy_trst_n
. Where does that belong in this sequence?