The build system now reflects the different build items. To do this, python build nodes now expect a view input and it passes that input into the verilog generator instantiation. This allows different views to have different configuration packages given our current approach. I've also fixed (unless there are new .md files) the lack of rebuild on JTAG register change by adding the JTAG markdown tables as Input nodes on the build graph.
Added the FFE and MSLD verilog into the vlog/new_chip_src branch. Cleaned up unnecessary files from the the chip_src branch.
Manually attached the appropriate packages if the dependency system can't find them.
There is a lot of smaller details but:
The build system now reflects the different build items. To do this, python build nodes now expect a view input and it passes that input into the verilog generator instantiation. This allows different views to have different configuration packages given our current approach. I've also fixed (unless there are new .md files) the lack of rebuild on JTAG register change by adding the JTAG markdown tables as Input nodes on the build graph.
Added the FFE and MSLD verilog into the vlog/new_chip_src branch. Cleaned up unnecessary files from the the chip_src branch.
Manually attached the appropriate packages if the dependency system can't find them.