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StanfordVLSI / dragonphy2

Open Source PHY v2
Apache License 2.0
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Add pi_ctl valid flag signal to DCORE #75

Closed sjkim85 closed 4 years ago

sjkim85 commented 4 years ago

Acore has been updated to remove the clk_cdr and it has to take a single bit flag "ctl_valid" . DCORE should be updated to generate this flag.

sgherbst commented 4 years ago

Looks like this task is still open. Note that dragonphy_top needs to be updated to integrate this change -- not only to add the port to idcore, but also to edit these lines of code: https://github.com/StanfordVLSI/dragonphy2/blob/7d83b86a16385eef1d3e2355eaadd7b7c22e9c23/vlog/new_chip_src/top/dragonphy_top.sv#L122-L125

zamyers commented 4 years ago

Finished when the mflowgen PR occurred a few days ago. Wired the PI Wait on Reset Signal to the port.