This PR aims to get the regression tests passing with the MDLL integrated into the top level. The changes I made were pretty minor:
In the MDLL Markdown file, rstn was changed to rstn_jtag to match with the MDLL JTAG interface definition.
Added missing port clk_b to the input_buffer stub.
Added missing wire definitions mdll_clk_refp, mdll_clk_refn, mdll_clk_monp, mdll_clk_monn to the top level.
Updated dragonphy/views.py to define `SIMULATION for the MDLL when running simulations and to use a stub for the MDLL when running synthesis.
`ANALOG_WIRE is converted to `real_t for consistency with the rest of the design. Modules in the MDLL that used `ANALOG_WIRE now `include "iotype.sv", which defines the `real_t macro.
mdll_param.vh (which defined `ANALOG_WIRE) is removed, as is the part of mdll_pkg.sv that redefined the `ANALOG_WIRE macro.
This PR aims to get the regression tests passing with the MDLL integrated into the top level. The changes I made were pretty minor:
rstnwas changed torstn_jtagto match with the MDLL JTAG interface definition.clk_bto theinput_bufferstub.mdll_clk_refp,mdll_clk_refn,mdll_clk_monp,mdll_clk_monnto the top level.dragonphy/views.pyto define`SIMULATIONfor the MDLL when running simulations and to use a stub for the MDLL when running synthesis.`ANALOG_WIREis converted to`real_tfor consistency with the rest of the design. Modules in the MDLL that used`ANALOG_WIREnow`include "iotype.sv", which defines the`real_tmacro.mdll_param.vh(which defined`ANALOG_WIRE) is removed, as is the part ofmdll_pkg.svthat redefined the`ANALOG_WIREmacro.