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StanfordVLSI / dragonphy2

Open Source PHY v2
Apache License 2.0
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increase PI bitw from 4 to 5 #84

Closed bclim closed 4 years ago

bclim commented 4 years ago

The phase interpolation bit-width in the MDLL is increased from 4 to 5. The jtag register and mdll_pkg parameter values are updated accordingly.

sgherbst commented 4 years ago

@bclim Thanks for this PR. Would you mind merging in the latest changes from the master branch?

bclim commented 4 years ago

@sgherbst I'll do it after the review.

bclim commented 4 years ago

@sjkim85 yet see the issue ?