Analog core5

[sjkim85]

V2T_clock_gen.sv is modified to fix the en_sync sequence issue. Now, data sequence at adc output looks good but it still looks wired after dcore. I want @standanley to look at this

[sjkim85]

@standanley , Can merge this to master?

[sjkim85]

@standanley , Can you merge this to master?

[standanley]

I just added a commit to change the en_sync chain so the signals should be in order. I am surprised to see that the AC test was passing because it looks like somebody already got rid of the magic re-ordering with the old en_sync chain. Was there a different change made that affected the ordering of ADC clocks?

[sjkim85]

@standanley I've changed the index ordering back to normal in order to test the fixed version in this PR. That's the only change I have made in testbench

[codecov-io]

Codecov Report

Merging #96 into master will not change coverage. The diff coverage is n/a.

@@           Coverage Diff           @@
##           master      #96   +/-   ##
=======================================
  Coverage   22.26%   22.26%           
=======================================
  Files          33       33           
  Lines        1909     1909           
=======================================
  Hits          425      425           
  Misses       1484     1484           

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[standanley]

I made a change to the default values for the config register codes for the retimer. I think before there was a problem with different ADCs having different latency. For me, this fixes issues with top_i.idcore.adcout_retimed when I look at the waveforms.

It does not affect the AC test because that pulls data from before the retimer.

[sjkim85]

Thanks for your work. As you know, we have to run AC test with final output of dcore (input to SRAM) eventually.

[zamyers]

LGTM