Closed sgherbst closed 4 years ago
Merging #97 into master will decrease coverage by
0.04%
. The diff coverage is100.00%
.
@@ Coverage Diff @@
## master #97 +/- ##
==========================================
- Coverage 22.26% 22.22% -0.05%
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Files 33 33
Lines 1909 1908 -1
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- Hits 425 424 -1
Misses 1484 1484
Impacted Files | Coverage Δ | |
---|---|---|
dragonphy/views.py | 82.78% <100.00%> (-0.14%) |
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This PR covers a bunch of updates related to synthesis, and also updates the top-level pinout.
clk_cgra
. This is a gated version ofclk_adc
that is enable with the JTAG biten_cgra_clk
(default is that it is disabled)freq_lvl_cross
andramp_clock
since we didn't get themset_dont_touch_network
is removed in many places because we do want the synthesis tool to insert buffers on most internal clocks for this tapeoutmax_transition
constraints set to values that are appropriate for their frequencies, and all black boxes have drive / loading information.ADK_DRIVING_CELL
to fix an issue with capacitance units and improve portability.analog_core
QTM.
for interfaces but flatten busses).clk_adc
(exploring more complex possibilities but wanted to submit this PR first)ext_clk
is considered a fake 1 GHz input for the purpose of the QTM. In the QTM,clk_adc
has no relation toext_clk
, but the constraints usecreate_clock
to define identical clocks forext_clk
andclk_adc
(except themax_transition
forext_clk
is much shorter because it is really an 8 GHz clock)