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StanfordVLSI / dragonphy2

Open Source PHY v2
Apache License 2.0
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Flatten port names in analog_core + PnR updates #98

Closed sgherbst closed 4 years ago

sgherbst commented 4 years ago

Summary

This PR resolves an issue with the port names for analog_core being generated in the synthesis step. In addition, it pulls in some recent updates to PnR scripts.

Details

  1. The critical update has to do with how flattening is implemented. I experimented with several possibilities and found this seems to work: use a verilog stub for analog_core to get the design to elaborate. Then, use change_names to modify the ports of analog_core prior to linking the *.lib file containing the QTM for analog_core.
  2. Name flattening has been applied to constraints TCL script
  3. Name flattening has been applied to the analog_core QTM. In addition, I found there were some obsolete pins in the QTM, so those have been removed.
  4. BuildKite now saves more artifacts from the synthesis process for debugging purposes.

Notes on changes merged in from other branches

  1. I don't think the clock_period parameter is actually used in the synthesis step because all clocks are defined in the constraints stage. Changing it from 1.0 to 0.8 shouldn't hurt, but I don't think it is used anywhere. (The constraints step has its own variable constr_main_per, which is used in several places)
  2. I noticed that flatten_effort has been changed to "3" -- not sure if this is related to timing or PnR requirements, but I just wanted to mention that it does not affect how ports on blocks like analog_core are renamed. That happens in the rtl step.