Stanlazy sp24_ece425_.release issues - Githubissues

Stanlazy / sp24_ece425_.release

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mp1 tie cell

#12 Stanlazy opened 2 months ago
0
use store for testing for mp2

#11 Stanlazy opened 2 months ago
0
no auto pnr in mp2

#10 Stanlazy opened 2 months ago
1
no poly routing

#9 Stanlazy opened 2 months ago
0
no pass transistor / pass gate in mp2

#8 Stanlazy opened 3 months ago
1
sim explaination

#7 Stanlazy opened 3 months ago
0
pc reset value

#6 Stanlazy opened 3 months ago
0
add spec about no routing above vdd and vss

#5 Stanlazy opened 4 months ago
0
analog simulation on hier cells need to have NC vdd and vss

#4 Stanlazy opened 4 months ago
0
mp0 verdi

#3 Stanlazy closed 5 months ago
0
The MOS in diagram is not minimally sized

#2 Stanlazy closed 5 months ago
1
Add Verilog extraction and Verilog simulation in MP0 doc

#1 Stanlazy closed 5 months ago
1