A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Simulations with differen corner-library (`.lib ../.../cornerMOSlv_psp.lib mos_tt and ...ss ...ff ...fs ...sf`), what would You do? #144
if You want to make some simulations with differen corner-library (.lib ../.../cornerMOSlv_psp.lib mos_tt and ...ss ...ff ...fs ...sf), what would You do?
i can use a launcher.sym to set a lib-variable and then xschem netlist; xschem simulate but i didnt figured out, how to wait of the end of the simulation before update the lib-variable, and simulate again.
or i could use TCL to write different spice-netlists and run them in parallel (also without knowing when it ended)...
now it looks like:
and the possibility to load different .raw-files is REALLY great!
@olisnr