Netlist Inconsistency

[kwmartin]

I am trying to instantiate an 8 to 1 multiplexor with each of the 8 inputs and the output being a 24 bit word. The screen grab above (if it comes through) shows the schematic. The block is an array of 24 1 bit multiplexors. When netlisting with Spice, the netlist comes as I am hoping for where the select bits (each of the 8 select bits turns on input on) are connected to all of the 1-bit muxes. However, when netlisting with verilog only one of the select bits is connected to each mux, and the select bits are rotated through. I have included just a couple of lines for the two different cases to illustrate: Spice (which is what I want):

MX[23] ADDR_[7] ADDR_[6] ADDR_[5] ADDR_[4] ADDR_[3] ADDR_[2] ADDR_[1] ADDR_[0] IN0_[23] IN1_[23]
+ IN2_[23] IN3_[23] IN4_[23] IN5_[23] IN6_[23] IN7_[23] DAT[23] VDD VSS m1mx_8x1
MX[22] ADDR_[7] ADDR_[6] ADDR_[5] ADDR_[4] ADDR_[3] ADDR_[2] ADDR_[1] ADDR_[0] IN0_[22] IN1_[22]
+ IN2_[22] IN3_[22] IN4_[22] IN5_[22] IN6_[22] IN7_[22] DAT[22] VDD VSS m1mx_8x1

Verilog (which is different and not what I want):

M1MX_8X1  MX_23 (  ADDR_[7]  ,  IN0_[23]  ,  IN1_[23]  ,  IN2_[23]  ,  IN3_[23]  ,  IN4_[23]  ,  IN5_[23]  ,  IN6_[23]  ,  IN7_[23]  ,  DAT[23]  ,  VDD  );
M1MX_8X1  MX_22 (  ADDR_[6]  ,  IN0_[22]  ,  IN1_[22]  ,  IN2_[22]  ,  IN3_[22]  ,  IN4_[22]  ,  IN5_[22]  ,  IN6_[22]  ,  IN7_[22]  ,  DAT[22]  ,  VSS  );

I have tried a few different things such as 2-D buses, but so far I am having trouble getting the verilog correct. Thank you. P.S. If you direct me to the verilog netlist source I can try and play around myself.

[StefanSchippers]

You have two choices: 1) declare each data I/O pin in the symbol as D7[23:0], D6[23:0], ... D0[23:0], OUT[23:0] 2) Place 24 instances of the m1mx symbol, that is , give it a name like XMUX[23:0] or X1[23:0], whatever you like,

for option 2) see image.